Quote:
Originally Posted by The Lucas
... PWM outs are connected to a chip labeled U2, so that should be the final stage of the PWM generation (or it could just be a buffer). What signals the FPGA and DIO modules send to drive that IC, I am not sure.
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I'm certainly not the expert, but here is my understanding. The circuit for generating the various PWMs, along with safety overrides is in the FPGA. The FPGA clocks state data out to the DIO, which is versatile, but not terribly fast or high current. To have the current to drive the victors, the signal gets boosted in the side car.
The internal cRIO bus is clocked at 40MHz, so latency isn't much of an issue.
Greg McKaskle