Quote:
Originally Posted by Kevin Sevcik
Finally, a list of the FPGA/WPILib supported special peripherals, as best I can recall them. And all of this is without costing any processing power:
four, 4x quadrature encoders, with pulse width measuring
eight, 1x or 2x quadrature encoders or counters, with pulse width measuring
two, analog signal accumulators, which means two analog gyros
two, I2C buses (with two sidecars)
two, SPI buses (with two sidecars) plus chip selects (on Dig I/Os)
serial communications through the cRIO serial port
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One inaccuracy here. The SPI engine is routable to any DIO pins on either module... there is only one of them. The hardware supports streaming with 512 word buffers on both the send and receive side and buffer status interrupts (such as half full), but that is not implemented in the library yet. WPILib for LabVIEW supports single sample SPI transfers and WPILib for C++ has no support. This is a low priority system. Right now it seems there is little demand for it.