[Kevin Sevcik]

The diligent coders at NI willing, the Jaguars won't even need PWM control next year, because we'll be using the CAN interface on them. And they'll be doing closed-loop position, velocity, and current control. With integral encoder and limit switches that you'll be able to get feedback from through the CAN bus. Assuming, of course, that the gods of the GDC and FIRST don't step in after kickoff with rules against using the CAN bus.....

Ahem. Anyways, the FPGA itself can support base clock rates up to 40 MHz, but actual loop rates depend on the code you're implementing. So only the NI gurus with the secret password know how much faster they could bump the loop rates.