[Dave Flowerday]

Before you get too far down this path, have you done the research to verify that it is possible to bit-bang a serial port on the cRio? Bit-banging RS232 requires very precise timing that may be difficult to achieve on the cRio, depending on how quickly the signal gets through the FPGA and into the cRio, how quickly your timer ISR is called by the OS, how quickly an output pin really changes after you tell the FPGA to change it, etc.

I haven't done any experiments yet to see what these delays look like, but it wouldn't take much to screw up the tight timings necessary for serial, especially at higher baudrates.