[Russ Beavis]

The A/D converter resides in the 9201 module. I believe that there is a serial interface between the FPGA in the cRIO chassis and the converter in the 9201 module. The FPGA is hard-coded to simply stream conversion values from all 8 channels and store them on the FPGA for you to query.

Oversampling refers to using the full 62kish samples/sec that the FPGA acquires from each 9201 and averaging, for example, 1000 at a time to effectively produce 1000x the resolution. This CAN work but it requires that the low-level signal has > 5mV peak-to-peak noise and that the noise is somewhat well-behaved.

Eric's suggestion can work in many instances but it requires that your sensor be a little noisy (it's obviously a bit counterintuitive since noise is almost always undesirable). You should DEFINITELY give it a try.

The only downside to oversampling is that it's a filtering process. You won't get the full 31kHz bandwidth as you would when using the raw 62k sample/sec stream. How much bandwidth do you need? If you only need about 100 samples per second from the sensor, you could consider averaging about 300 samples at a time for 62k/(300*2) = 100Hz bandwidth. That could also, theoretically, reduce your resolution from 5mV to 5/300mV = 17uV.

I'd recommend that you give oversampling a chance!

Russ