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Unread 11-05-2009, 15:45
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Re: Failed attempt to explain JAG linearity

Quote:
Originally Posted by Joe Ross View Post
It was a Victor 884.

When I read through the jaguar docs, when you get into the CAN modes, there is both a voltage control mode and a current control mode. There was no mention of a pulse width control mode. If the Jaguar was in voltage control mode, that might explain the speed linearity.
I believe the voltage control mode simply converts a voltage input to a pwm command. There are provisions for a reference voltage input from a pot as well. I don't believe there is any voltage feedback that is used in a PID loop..only encoder or current.

If you look at hbridge.c there is some code that does this conversion:
Here is an excerpt when the input voltage g_lHBridgeV is >0.....

// Compute the PWM compare value from the desired output voltage.
// Limit the compare value such that the output pulse doesn't
// become too short or too long.
//
ulCompare = (((32767 - ((g_lHBridgeV * g_lHBridgeVMax) / 32767)) *
SYSCLK_PER_PWM_PERIOD) / 32767);

g_lHBridgeVMax=32767 so this essentially says that


ulCompare = (1 - voltage/32767)*SYSCLK_PER_PWM_PERIOD

ulCompare then sets the HW registers to generate a gate pulse for a given number of system clock counts.

I don't fully understand how these compare registers work but I'm guessing ulCompare sets a counter threshold on a system clock pulse counter. So if the voltage is zero then the counter never trips and the gates remain off. If the voltage is max or 32767 cnts then the ulCompare is zero and the gates are always on. Anything in between sets the duty pulse width.

Last edited by vamfun : 11-05-2009 at 16:04.