Thread: Failed attempt to explain JAG linearity
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Unread 18-05-2009, 21:00
Gdeaver Gdeaver is offline
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Re: Failed attempt to explain JAG linearity
I don't Know if this affects the discussion, but I believe a high side FET is left on durring the PWM off period. They are applying the PWM to the gate driver enable pin. For forward the gate driver A PWM input pin is set high and the chip enable set to high. The B Gate driver PWM input pin is set low and the PWM pulse is applied to the B gate driver enable. So in the off period the A high side FET is in an on state and both B side FETS are off. So does this mean the inductive spike is clamped to the battery voltage or just above with the Fet resistance?