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Unread 19-05-2009, 01:37
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Re: Failed attempt to explain JAG linearity

Quote:
Originally Posted by Gdeaver View Post
I don't Know if this affects the discussion, but I believe a high side FET is left on durring the PWM off period. They are applying the PWM to the gate driver enable pin. For forward the gate driver A PWM input pin is set high and the chip enable set to high. The B Gate driver PWM input pin is set low and the PWM pulse is applied to the B gate driver enable. So in the off period the A high side FET is in an on state and both B side FETS are off. So does this mean the inductive spike is clamped to the battery voltage or just above with the Fet resistance?
If I look at hbridge.c the way I intrepret the software switches is shown in the attached doc. When they say the minus side = LO then I thought the gates on the lo side were either on or off and the hi side minus gate was off. I could have these reversed. Look at this straw man and we will get full agreement on the configuration. I have only depicted the voltage input>0 drive state.

Update: the zip expands this to Chris config, Gdeaver config and an Al? config
Attached Files
File Type: doc Jag Hbridge Config.doc (39.0 KB, 33 views)
File Type: zip Jag Hbridge Configuration.rev1.zip (17.7 KB, 32 views)

Last edited by vamfun : 19-05-2009 at 03:40.