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Re: Encoder problem
The limit is because the cRIO FPGA can (currently) only allocate four, 4x encoder interfaces. The workaround is to declare your encoders as 1X or 2X (see WPILib documentation on how to do this); this forces the FPGA to implement your encoders as up/down counters, which have different FPGA implementations.
Which encoders should you keep as 4X and which should you implement as 1X or 2X? Generally, encoders that directly measure position (like your steering encoders) you should leave at 4X for the highest precision. Encoders that measure speed (your drive wheels and idler wheels) are often better off at 1X for several reasons. First, when timing the period between two edges longer amounts of time mean more accurate measurements because of the limitations of the timers. At 1X, the edge-edge time is 4 times as long as with 4X. Second, due to manufacturing and assembling tolerances, all both phases are often not exactly 90 degrees out of phase, and each phase is often not exactly at a 50% duty cycle. By only counting a certain edge (say, rising edge of phase A), you ignore these problems.
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