Quote:
Originally Posted by kamocat
It looks like it actually updates all 14 GPIO at the same time. Is this how the module is normally accessed?
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First of all, nice job on speeding it up, it's not always easy. But this is how it's usually done on microcontrollers, I'm not sure if it's the same way on the FPGA. But at least in micros, values are updated an entire register at a time, and it does not impact speed. Basically, the microcontroller is designed in such a way that it tells the port register what ALL of its values are in parallel (for speed), and it updates all 8 pins on the register almost simultaneously.
This is mainly for parallel communication, where you need to update all of the bits in the byte you're trying to send at the same time so you can tell the receiving end of the line when it can look for the new data. It's kind of just a precedent, and they've probably put that into the update protocols of the digital module itself (cRIO communicates to the digital module over a serial connection, that VGA-sized port at the bottom, so all data extraction is done inside the module).
This is all just inferences from working with other microcontrollers, and I know that the cRIO is a completely different animal, but the precedents probably still stand. I'm going to guess that the GPIO bank is made up of two registers coming off of the chip inside the digital module, which would kind of act like a "middle-man". If anyone here knows the actual construction of the cRIO modules, I would love to hear about it.