Quote:
Originally Posted by ubermeister
a) Encoders count much faster than this switch, so there must be some way to count quickly, namely offloading this task to the FPGA. My thought is to tell the cRIO to pretend that this switch is actually an encoder (non-quadrature), thus forcing the FPGA to count the pulses. The programmers say that this will not help, because we would still only be able to retrieve the count every 100 ms, gaining us no advantage. I say it will give us a 2x speed improvement, since we do not have to see both the rising and falling edge of the limit switch, only the falling edge. Also, it will prevent missing multiple pulses; you would miss at most 1 rather than having the pulses line up such that they are all missed. I'm pretty sure I'm right in this case, but some confirmation would be nice to help me convince them that this is a good idea.
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The FPGA also implements single channel counters.
You are correct that you should not try to poll any input quickly, as you'll be disappointed in the results.