[Greg McKaskle]

The cRIO FPGA is normally just another LabVIEW target. You write VIs for very low level I/O and simple computation, twiddle your thumbs for quite some time as the VHDL tool chain constructs the image, and then you deploy it to the FPGA.

When it executes, the FPGA has complete control of all module I/O and on the other end is user definable memory, typically called registers. They will contain configuration data for the FPGA, or results from the I/O. The registers are represented as front panel controls in LV, by the way.

The next layer of code is written using RT and runs on the cRIO. It accesses the registers and typically implements higher level control, monitoring, logging, user protocols, etc.

For FRC, the FPGA image contains the safety mechanism for shutting down all outputs, so it is used as binary, and acts as the I/O engine. When the cRIO is imaged, one part of that image is the FPGA bitmask. For FRC, the FPGA is responsible for all PWM generation, counters and encoders, analog averaging and oversampling, digital and analog triggers, I2C and SPI, and I'm sure I'm leaving out plenty of other tasks. This leaves the cRIO to the job of communications, scaling, configuring, control, vision, serial and CAN. This is still a very simplistic view of the system. If you are in Atlanta, there will likely be some more in depth presentations, and you can of course always drop by the booth. Or ask the more detailed questions here if you like.

Greg McKaskle