Quote:
Originally Posted by Chris Hibner
I'm not sure what you're saying here.
As far as I know, there is no cRIO code resetting the FPGA counter. My point was as follows (I didn't state it very clearly):
As long as:
1) the encoders are decoded by an interrupt handler in the FPGA
and
2) the cRIO samples the FPGA counter fast enough such that it cannot do a complete overflow cycle (e.g. the encoder cannot rotate more than 65536 counts (if 16-bit counter is used) in one cRIO sample).
and
3) The WPI code uses the difference between the current FPGA count and the previous FPGA count (instead of the absolute FPGA).
THEN
FPGA overflow does not matter, since the two's compliment math in the subtraction in step 3 above will work even in an overflow situation. You can run the cRIO for three years (not 3 minutes) and you will not see an issue from the FPGA counter. You will, however, eventually overflow the double-precision distance calculation from the WPI code, but that has nothing to do with the FPGA overflowing.
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OK, my bad, in my haste I didn't look at your code carefully enough.
By the way, I
love your sig line. Very clever. Is that an original ?
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