Quote:
Originally Posted by Greg McKaskle
The deep diving, at least in LV is the NIFPGA interface. This exposes accumulators, triggers, and other raw forms of I/O which the general and wading layers are built from. It should allow for alternate implementations, alternate frameworks, and external sensors and actuators to be added in. At the moment this is as deep as the pool can go since the FPGA implements the safety mechanisms, and it doesn't seem appropriate for teams to modify the safety layer. Ideally, that layer will be opened up too, showing how to do encoders, PWM generation, triggers, integrators, etc on an FPGA.
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Is there a way that any of the implementation can be exposed?
Maybe only the things you mentioned (encoders, PWM, triggers, etc.) without comprimising any of the safety layer.
Even a screen shot would be better then the virtual "black box" that it is now.
Some knowledge of how the system works would help diagnose some issues, even if they can't be directly fixed (indirectly through bug reports).