Quote:
Originally Posted by Greg McKaskle
If you are pretty convinced there is a bug in something, I suppose we could give out a screenshot to help get to the bottom of it, but again, since this is the safety protocol, we wouldn't want any enterprising team to "optimize" it, resulting in someone getting hurt. So whatever we'd do we'd keep FIRST in the loop.
Trust me, NI and especially Xilinx would like you to have access.
Greg McKaskle
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I haven't noticed any bugs, at least in what I have experimented with,
but as a non-FIRST project I would like to start working with a FPGA.
I understand the concern for safety, though it shouldn't be in every VI especially in the ones used for input (Accumulator, encoder, etc.).
Could the ones that wouldn't comprimise the safety layer be released somehow, or somewhere(Firstforge)?