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Originally Posted by jhersh
If you are looking at your proposed same edge flag, then you have to read before the next edge or you've lost the information. Hence my statement that you would have to read fast enough to catch every edge in order to make use of such a bit.
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This is like trying to decode the encoder without interrupts using fast reads...just seems you couldn't do it reliably.
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Perhaps I could make the same edge event set the stalled bit immediately, since a same edge represents a stop (except in the ridiculous noise case).
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Thats an idea.. or maybe make DIR flag a two bit output... the first bit is DIR, the second is LAST_DIR
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As Alan stated, use a position controller, which doesn't use the rate output, it uses the position output.
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This of course depends on the dynamics of the open loop plant. If there is sufficient loop lag, then usually a rate term is required to place the closed loop poles at the optimum values.
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Chris...Can you pipe the DIR flag into the pipeline so there would be 0's and 1's in the pipe line ? If so, couldn't you construct a recursive pipeline sum by summing the 1's in the pipeline and then computing a signed_sum = 2*(sum of 1's) - max_count. Then in GetRate() compute rate = (signed_sum )/period rather than 1/(period/max count). The summation would take a little extra time... not sure what the FPGA could do to optimize this.
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Joe...What is the benefit to this? Just cancelling out one set of rates for each dir change?
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The signed_sum is just the net count (net position change) over the period. Isn't this what you want for a moving average that isn't zero reset?