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Unread 11-01-2007, 08:19
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TX2IE & RCIF

#ifndef __ifi_utilities_h_
#define __ifi_utilities_h_

#ifdef _SNOOP_ON_COM1 /* FOR FUTURE USE */
#define RXINTF PIR3bits.RC2IF
#define RXINTE PIE3bits.RC2IE
#define TXINTF PIR3bits.C
#define TXINTE PIE3bits.TX2IE
#define RCSTAbits RCSTA2bits
#define RCSTA RCSTA2
#define TXSTA TXSTA2
#define TXREG TXREG2
#define RCREG RCREG2
#define SPBRG SPBRG2
#define OpenUSART Open2USART
#else
#define RXINTF PIR1bits.RCIF
#define RXINTE PIE1bits.RCIE
#define TXINTF PIR1bits.TXIF
#define TXINTE PIE1bits.TXIE
#define RCSTAbits RCSTA1bits
#define RCSTA RCSTA1
#define TXSTA TXSTA1
#define TXREG TXREG1
#define RCREG RCREG1
#define SPBRG SPBRG1
#define OpenUSART Open1USART
#endif

What exactly are these values entered to the macros???? We couldn't find any RCIF on the computer, is it something on the RC system?
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Unread 11-01-2007, 08:45
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Re: TX2IE & RCIF

They are giving sane names "TXINTF/INTE" to the microcontroller names for the same signals. IE is interrupt enable, IF is interrupt flag (indicating the interrupt has occurred).

The specific macros you've shown are things you do not want to modify or highly unexpected things will happen

--Eric
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Unread 11-01-2007, 08:56
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Re: TX2IE & RCIF

TX2IE
According to the datasheet, TX2IE is the fourth bit of Peripheral Interrupt Enable register 3 (PIE3). this bit is used as an enable bit for a USART on the PIC.

If it is set to 1, the bit is set and the interrupt is active. if it is set to 0, it is not active.

Quote:
TX2IE: EUSART2 Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
In plain English, when TX2IE is enabled, interrupts on the bit TX2IF are generated whenever the transmit buffer is empty.

RCIF
Likewise, RC1IF is bit 5 of the Peripheral Interrupt Request register 1 (PIR1).
this bit is used as a receive interrupt flag bit for a USART
Quote:
RC1IF: EUSART1 Receive Interrupt Flag bit
1 = The EUSART1 receive buffer, RCREG1, is full (cleared when RCREG1 is read)
0 = The EUSART1 receive buffer is empty
So, when RC1IE is enabled, interrupts on RC1IF are generated whenever the receive buffer is full.
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Unread 11-01-2007, 09:05
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Re: TX2IE & RCIF

What is this "Interupt"?
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Unread 11-01-2007, 09:18
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Re: TX2IE & RCIF

An interrupt is a hardware signal saying that something has changed and requires attention immediately. There is then software that clears the interrupt flag and then handles the event.
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