Cartesian to angle

[Jogo]

from the +y axis? atan2(-x,y) seems to do the trick.

[Ether]

Originally Posted by Jogo

from the +y axis? atan2(-x,y) seems to do the trick.

atan2(-x,y) gives you angles counter-clockwise from the +Y axis.

[Ether]

Just to be clear, all references to atan2 in any of my posts, UOS, refer to the standard definition of the order of the parameters, not the reversed-order of, say, Microsoft Excel spreadsheet.

[Dmentor]

atan2(-x,-y)+pi seems to avoid excessive logic.

[Ether]

Originally Posted by Dmentor

atan2(-x,-y)+pi seems to avoid excessive logic.

That's what I use. Here's a cheatsheet for other angle choices.

[davidthefat]

A look up table?

[AdamHeard]

Originally Posted by davidthefat

A look up table?

Why? That's terribly cumbersome compared to the methods already posted.

[davidthefat]

Originally Posted by AdamHeard

Why? That's terribly cumbersome compared to the methods already posted.

Well, it takes less clock cycles to just retrieve data from an array compared to calculating the angle on the fly. Even though a look up table does take up considerable amount of space in the RAM (Not really since we are dealing with 64 MB of RAM...) Also given the level of accuracy we only really need, about ± pi/180 radian. I think it should be fine.

[AdamHeard]

Originally Posted by davidthefat

Well, it takes less clock cycles to just retrieve data from an array compared to calculating the angle on the fly. Even though a look up table does take up considerable amount of space in the RAM (Not really since we are dealing with 64 MB of RAM...) Also given the level of accuracy we only really need, about ± pi/180 radian. I think it should be fine.

The cycles are a nonissue on the cRIO, and using the function is substantially less code/setup time.

[Ether]

Originally Posted by davidthefat

Well, it takes less clock cycles to just retrieve data from an array compared to calculating the angle on the fly.

Where do you get your information ?

[EricVanWyk]

Originally Posted by Ether

Where do you get your information ?

You must spread some Reputation around before giving it to Ether again.

[PAR_WIG1350]

Originally Posted by davidthefat

Well, it takes less clock cycles to just retrieve data from an array compared to calculating the angle on the fly. Even though a look up table does take up considerable amount of space in the RAM (Not really since we are dealing with 64 MB of RAM...) Also given the level of accuracy we only really need, about ± pi/180 radian. I think it should be fine.

Wait, the crio only has 64 MB of ram? Yes, it does indeed. You learn something new every day I guess.

[jhersh]

Originally Posted by PAR_WIG1350

Wait, the crio only has 64 MB of ram? Yes, it does indeed. You learn something new every day I guess.

... and the new cRIO-FRC2 has 128 MB of RAM.

[James Critchley]

Fantastic!

I though you were going to post the trig logic to do all of the calculations. "atan2" is certainly the way to go, transforming coordinates before using it is great.

I need to look at a clock again... right hand rule = CCW!!! See my earlier post.


From a readability perspective, consider defining a macro statement such that.

angle = HEADING(0,0);



atan2(0,0) is undefined in the standard. So for cross platform use, you should check for this as an arbitrary compiler can throw an exception.

if y == 0.0 then y = 1e-8.

Assuming you aren't working with nano-bots this will do nicely and leave your (0,0) point at 0. Unfortunately this adds a comparison operation which, as implied here, are commonly the most costly operations and what you are trying to avoid. This is a prety good arguement for changing the standard.


I did some reading, and as Ether pointed out, ALL recent Intel chips define (0,0) as 0 and this is on the chip and part of the FPU. If you use a look-up table, you need an unbounded (or large) 2D table in x and y... You can manage this by normalization or conversion to a one dimensional problem but atan2 solves it right there in the silicon. There are a host of other issues with the look-up table but the one that strikes me is the effort associated with continually moving a table back and forth through the layers of cache on the chip (Cache is MUCH smaller than RAM). It's not a good option and should not be faster (coding or execution with other intensive code in the loop) or portable to higher resolution applications. In the interest of exhausting all alternatives, the look-up table certainly is "out of the box" and I like it. Keep up the good work!

With the Intel FPU, most modern PC's and Macs will get (0,0) = 0 "right" provided the compiler actually accesses the FPU directly for this calculation (that would be most compilers including gcc). But what does the cRIO do? Is the FPGA intel based? Looks like "Xilinx Virtex" is a custom processor for FPGA? So you need documentation of a firm commitment to define the result as 0, or you need to test and a re-test every time the chip is upgraded which could happen without a "model" change to cRIO.

[JamesBrown]

Originally Posted by James Critchley

Fantastic!
With the Intel FPU, most modern PC's and Macs will get (0,0) = 0 "right" provided the compiler actually accesses the FPU directly for this calculation (that would be most compilers including gcc). But what does the cRIO do? Is the FPGA intel based? Looks like "Xilinx Virtex" is a custom processor for FPGA? So you need documentation of a firm commitment to define the result as 0, or you need to test and a re-test every time the chip is upgraded which could happen without a "model" change to cRIO.

There seems to be a lot of confusion as to what an FPGA is, specifically what the FPGA in the cRIO is, if anyone is so inclined it may be of value for someone to write up a description about it. It seems that despite being tucked well within NI's system there is a lot of curiosity about it.

To answer quickly FPGA's and processors are inherently different things. an FPGA or field programmable gate array is basically a huge array of gates, basically if you could take millions of nand gates and organize them in an array such that you can combine them in any way you like you would have the functional equivalent of an FPGA. Obviously the execution of an FPGA is a bit mor ecomplicated but you can visualize what is happening this way. By combining the gates in the FPGA in different ways you can create any logic circuits within the chip, including processors. The Xilinx Virtex is simply the family of FPGA's the one on board the cRIO belongs to. Xilinx is the manufacturer, Virtex is the family. Xilinx does have a few different soft core processors (processors created wthin the FPGA) that you can load onto the chip (MicroBlaze, PicoBlaze etc.). I do not howeve know whether these (or any thing simmilar) are implemented in the FPGA, I would guess they are not.