FRC FPGA usage

[apalrd]

Today, I had a discussion with Eric Yahrmatter about the cRio, specifically the FPGA. We talked about the possibility of pushing hard RT tasks (especially PID control loops) to the FPGA, relieving the processor of the hard RT tasks and allowing it to do more functionally advanced things without worrying about bogging down the hard RT tasks.

Does anyone have opinions on opening the FPGA to teams? Opening the FPGA to hard RT tasks (like PID controls) would allow more freedom on the processor to implement processor-intensive tasks (such as vision processing) without worrying about the consequences of full CPU usage, and would make the control loops more stable and faster response at the same time.

If allowed, I would recommend that it be discouraged to teams without a good programming resource, as it could be more trouble than it is worth unless the programmer knows exactly what they are doing.

In case anyone is in the dark and has no idea what I am talking about:
-An FPGA (Field Programmable Gate Array) is essentially configurable hardware, allowing you to essentially write hardware. FPGA's can be used for very fast hard multi-threaded RT tasks, as blocks of hardware can execute synchronously - there is no single processor executing a single instruction. They are good for doing fast math operations in parallel.
-The FPGA in the cRio interfaces the hardware IO to the processor. In order to read the IO, there must be FPGA code which does the reading and returns the result to the processor (likewise in reverse). Currently, FIRST provides an image which must be used, which defines some standard IO (raw IO, PWM output, encoder/counters, accumulators, etc.)

Please note that we have not yet received our 2012 beta test information. This is pure speculation.