FRC FPGA usage

[jhersh]

The FPGA is pretty full as it is today. It fails to meet timing 30% of the times it's built. There is no vision processing in the FPGA today. Given that the camera teams use is Ethernet based and not a raw sensor connected directly to the FPGA I/O, the cost of getting the image into the FPGA generally outweighs any processing benefit.

As for PID, the PWM interface to the motor controllers is so slow that the RT processor can easily keep up even when heavily taxed, assuming task priorities are assigned reasonably. The CAN interface is not directly accessible by the FPGA, so that route won't benefit either.

So far I haven't heard any compelling reasons to make the FPGA design open. However, the fact that the safety mechanisms are mostly implemented in the FPGA is a very good reason not to open the design. Potentially future technologies like partial reconfiguration would remove that concern.

I'm always open to evaluating specific feature requests for the FPGA design.

-Joe