US Digital Encoders - How many CPR?

[sanddrag]

Forgive me, I'm not a programmer and my students won't be here until this afternoon. This is a rather simple question but I couldn't find the answer. Can we use any number of count US Digital Encoders with Java? The students asked me to purchase 250 count, but I'm wondering if some lesser count would be better for high speed things. Is Java set up to use any number of count encoders? We may need to read three simultaneously if that makes any difference.

[Joe Ross]

The FPGA can decode approximately 153k edges per second and can handle 8 single channel counters and 4 two channel encoders simultaneously (each at 153k). If you're using a quaderature encoder (with four edges per count, the max is approximately 38k). This is the same across all languages. Neither the FPGA or the code care how many counts the encoder is, as long as it doesn't exceed 153k/38k limit. If you're running a shooter that only runs in one direction, you only need to use a single channel of the encoder with a counter object.

There is good discussion in the following thread about how the FPGA's clock rate affects the noise in measuring periods at high speed. http://www.chiefdelphi.com/forums/sh...d.php?t=112193. I recommend playing with the spreadsheet that Ether posted in that thread. The averaging feature used in that spreadsheet isn't user-accessible in Java, without recompiling WPILib. It wouldn't be hard to add, however. Without using averaging, it is better to use a lower count encoder.

[sanddrag]

Thanks for the help Joe. You posted just in time before I had to put the order in.

[Ether]

Originally Posted by Joe Ross

The FPGA can decode approximately 153k edges per second and can handle 8 single channel counters and 4 two channel encoders simultaneously (each at 153k). If you're using a quaderature encoder (with four edges per count, the max is approximately 38k).

The quadrature encoder uses two separate DIO channels. On each channel, there are only 2 edges per cycle (one rising and one falling).

So shouldn't the max be 153K/2 instead of 38K? Or do the two FPGA channels get tied together somehow when you configure them for quadrature decoding, so that each channel is no longer capable of 153K?

[Joe Ross]

Originally Posted by Ether

The quadrature encoder uses two separate DIO channels. On each channel, there are only 2 edges per cycle (one rising and one falling).

So shouldn't the max be 153K/2 instead of 38K? Or do the two FPGA channels get tied together somehow when you configure them for quadrature decoding, so that each channel is no longer capable of 153K?

I got that from an old post on the NI forums from Joe Hershberger. https://decibel.ni.com/content/message/12541#12541 It probably has to do with quadrature detection for direction. It seems like it would need one clock in each of the 4 states.

[Ether]

Originally Posted by Joe Ross

I got that from an old post on the NI forums from Joe Hershberger. https://decibel.ni.com/content/message/12541#12541 It probably has to do with quadrature detection for direction. It seems like it would need one clock in each of the 4 states.

Thanks. I'll check with Joe and share what I find out.

[NotInControl]

Originally Posted by Ether

The quadrature encoder uses two separate DIO channels. On each channel, there are only 2 edges per cycle (one rising and one falling).

So shouldn't the max be 153K/2 instead of 38K? Or do the two FPGA channels get tied together somehow when you configure them for quadrature decoding, so that each channel is no longer capable of 153K?

My understanding is that the 4 quadrature decoders just use a single counter, counting rising and falling edges on two discrete lines which is why it is 38K max (and keeps track of A and B phase for direction). I do not believe it use two separate counters for each DIO channel.

[Ether]

Originally Posted by NotInControl

My understanding is that the 4 quadrature decoders just use a single counter, counting rising and falling edges on two discrete lines which is why it is 38K max (and keeps track of A and B phase for direction). I do not believe it use two separate counters for each DIO channel.

No. A quadrature encoder uses 2 DIO channels. Each channel gets polled synchronously by the FPGA at 153KHz. Each channel counts its 720 edges at 153Khz.

But the encoder will not work if the elapsed time between rising edge on channel A and rising edge on channel B (or vice versa) exceeds 1/153KHz seconds, because the FPGA won't be able to tell which came first. That's where the 38K limit comes from.