US Digital Encoders - How many CPR?

[Ether]

Originally Posted by Joe Ross

The FPGA can decode approximately 153k edges per second and can handle 8 single channel counters and 4 two channel encoders simultaneously (each at 153k). If you're using a quaderature encoder (with four edges per count, the max is approximately 38k).

The quadrature encoder uses two separate DIO channels. On each channel, there are only 2 edges per cycle (one rising and one falling).

So shouldn't the max be 153K/2 instead of 38K? Or do the two FPGA channels get tied together somehow when you configure them for quadrature decoding, so that each channel is no longer capable of 153K?