Go to Post It means Dave Lavery isn't on the Game Design Committee this year. If he were, you probably would have found a banana instead. - Alan Anderson [more]
Home
Go Back   Chief Delphi > Technical > Programming > NI LabVIEW
CD-Media   CD-Spy  
portal register members calendar search Today's Posts Mark Forums Read FAQ rules

 
Reply
Thread Tools Rate Thread Display Modes
  #1   Spotlight this post!  
Unread 16-02-2013, 15:13
Ether's Avatar
Ether Ether is offline
systems engineer (retired)
no team
 
Join Date: Nov 2009
Rookie Year: 1969
Location: US
Posts: 8,100
Ether has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond repute
logic gates question


Could this be implemented in LabVIEW? And if so, what would it do?

note: the intent of the small circle on the bottom input of each AND gate is that the bottom input is inverted


Attached Thumbnails
Click image for larger version

Name:	logic_gates_question.png
Views:	87
Size:	14.8 KB
ID:	14047  

Last edited by Ether : 16-02-2013 at 17:15. Reason: added note
Reply With Quote
  #2   Spotlight this post!  
Unread 16-02-2013, 16:16
Nirvash's Avatar
Nirvash Nirvash is offline
Registered User
AKA: Bryan
FRC #4676
Team Role: Programmer
 
Join Date: Feb 2011
Rookie Year: 2011
Location: Orland Park, IL
Posts: 221
Nirvash has a spectacular aura aboutNirvash has a spectacular aura about
It can be, I coded it up quickly while I was waiting for something, but I'm not sure what it is trying to do.

The second set of ANDs require the last output to be True, so unless you initialized the output to be true, the Ands would never let the code output True.
__________________
Team 3488 - Electrical Lead/Programming Lead 2011-2013
Team 4676 - Electrical/Programming Mentor 2013-Present
Reply With Quote
  #3   Spotlight this post!  
Unread 16-02-2013, 17:16
Ether's Avatar
Ether Ether is offline
systems engineer (retired)
no team
 
Join Date: Nov 2009
Rookie Year: 1969
Location: US
Posts: 8,100
Ether has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond repute
Re: logic gates question


note: the intent of the small circle on the bottom input of each AND gate is that the bottom input is inverted


Reply With Quote
  #4   Spotlight this post!  
Unread 16-02-2013, 17:47
Greg McKaskle Greg McKaskle is offline
Registered User
FRC #2468 (Team NI & Appreciate)
 
Join Date: Apr 2008
Rookie Year: 2008
Location: Austin, TX
Posts: 4,752
Greg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond repute
Re: logic gates question

I wasn't sure who the question was for. Here is what it looks like in LV if you use the growable logic nodes.

I'll let others do the implementation to see the end result. There are many many ways to write this by the way.

Greg McKaskle
Attached Thumbnails
Click image for larger version

Name:	Clipboard 1.png
Views:	59
Size:	41.5 KB
ID:	14052  
Reply With Quote
  #5   Spotlight this post!  
Unread 16-02-2013, 18:01
Omar's Avatar
Omar Omar is offline
Registered User
no team
Team Role: Mentor
 
Join Date: Dec 2008
Rookie Year: 2008
Location: Huntsville, AL
Posts: 122
Omar is a glorious beacon of lightOmar is a glorious beacon of lightOmar is a glorious beacon of lightOmar is a glorious beacon of lightOmar is a glorious beacon of light
Re: logic gates question

Greg beat me with the exact implimentation for a toggle

Here is a simple one that has been posted before

Click image for larger version

Name:	Toggle2.png
Views:	74
Size:	11.4 KB
ID:	14053
__________________
Omar
Reply With Quote
  #6   Spotlight this post!  
Unread 16-02-2013, 18:25
Nirvash's Avatar
Nirvash Nirvash is offline
Registered User
AKA: Bryan
FRC #4676
Team Role: Programmer
 
Join Date: Feb 2011
Rookie Year: 2011
Location: Orland Park, IL
Posts: 221
Nirvash has a spectacular aura aboutNirvash has a spectacular aura about
Quote:
Originally Posted by Ether View Post

note: the intent of the small circle on the bottom input of each AND gate is that the bottom input is inverted


Ah, missed that first time I looked at it.
__________________
Team 3488 - Electrical Lead/Programming Lead 2011-2013
Team 4676 - Electrical/Programming Mentor 2013-Present
Reply With Quote
  #7   Spotlight this post!  
Unread 16-02-2013, 20:15
Ether's Avatar
Ether Ether is offline
systems engineer (retired)
no team
 
Join Date: Nov 2009
Rookie Year: 1969
Location: US
Posts: 8,100
Ether has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond repute
Re: logic gates question

Quote:
Originally Posted by Omar View Post
Greg beat me with the exact implimentation for a toggle

Here is a simple one that has been posted before

Attachment 14053
That's very concise.

@ Greg: how much different is the code that LabVIEW generates for the following two different approaches?

http://www.chiefdelphi.com/forums/at...3&d=1361055503

http://www.chiefdelphi.com/forums/at...8&d=1360772515


Reply With Quote
  #8   Spotlight this post!  
Unread 17-02-2013, 00:55
Cecil's Avatar
Cecil Cecil is offline
Registered User
AKA: Alex Hummel
FRC #2010 (Lightning Bots)
Team Role: Mentor
 
Join Date: Dec 2008
Rookie Year: 2006
Location: Champion
Posts: 343
Cecil is a splendid one to beholdCecil is a splendid one to beholdCecil is a splendid one to beholdCecil is a splendid one to beholdCecil is a splendid one to beholdCecil is a splendid one to beholdCecil is a splendid one to behold
Re: logic gates question

Quote:
Originally Posted by Greg McKaskle View Post
I wasn't sure who the question was for. Here is what it looks like in LV if you use the growable logic nodes.
Whoah, there are growable logic nodes? Time to go get rid of the 3 and statements I have hooked together...
__________________
I'm right 90% of the time, so why worry about the other 3%?
Reply With Quote
  #9   Spotlight this post!  
Unread 17-02-2013, 08:18
Greg McKaskle Greg McKaskle is offline
Registered User
FRC #2468 (Team NI & Appreciate)
 
Join Date: Apr 2008
Rookie Year: 2008
Location: Austin, TX
Posts: 4,752
Greg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond repute
Re: logic gates question

The LV compiler supports optimization transforms, but I don't expect there to be one that will turn the select and negate into the XOR. So I expect the XOR to be just a bit more efficient. I put the code into timing sequences and ran it 100,000,000 times and indeed, at least for intel code gen, the XOR is just a bit faster.

Greg McKaskle
Reply With Quote
  #10   Spotlight this post!  
Unread 17-02-2013, 16:44
Ether's Avatar
Ether Ether is offline
systems engineer (retired)
no team
 
Join Date: Nov 2009
Rookie Year: 1969
Location: US
Posts: 8,100
Ether has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond repute
Re: logic gates question

Quote:
Originally Posted by Greg McKaskle View Post
The LV compiler supports optimization transforms, but I don't expect there to be one that will turn the select and negate into the XOR. So I expect the XOR to be just a bit more efficient. I put the code into timing sequences and ran it 100,000,000 times and indeed, at least for intel code gen, the XOR is just a bit faster.
Thanks Greg. I realize the difference, if any, is likely miniscule, but would it be reasonable to assume (based on your testing above) that the bottom sketch in the attached PNG is also slightly more efficient than the top one?
Attached Thumbnails
Click image for larger version

Name:	gt vs and.png
Views:	30
Size:	10.3 KB
ID:	14069  

Last edited by Ether : 17-02-2013 at 18:28. Reason: forgot to add the sketch
Reply With Quote
  #11   Spotlight this post!  
Unread 17-02-2013, 18:20
Greg McKaskle Greg McKaskle is offline
Registered User
FRC #2468 (Team NI & Appreciate)
 
Join Date: Apr 2008
Rookie Year: 2008
Location: Austin, TX
Posts: 4,752
Greg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond repute
Re: logic gates question

My testing showed that at least on Intel, the top one that used XOR was more efficient.

I rewrote the other to use a case statement instead of a select and it was then the fastest. Selects tend to execute both the true and false and then select the appropriate one whereas case statements will only execute one or the other.

But at this level for toggle on a button on a joystick, we are in the weeds. Write what is readable.

Greg McKaskle
Reply With Quote
  #12   Spotlight this post!  
Unread 17-02-2013, 18:33
Ether's Avatar
Ether Ether is offline
systems engineer (retired)
no team
 
Join Date: Nov 2009
Rookie Year: 1969
Location: US
Posts: 8,100
Ether has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond reputeEther has a reputation beyond repute
Re: logic gates question

Quote:
Originally Posted by Greg McKaskle View Post
My testing showed that at least on Intel, the top one that used XOR was more efficient.
Sorry, my previous post made no sense since I forgot to attach the PNG it was referencing. It's attached now:

http://www.chiefdelphi.com/forums/sh...5&postcount=10

Quote:
I rewrote the other to use a case statement instead of a select and it was then the fastest. Selects tend to execute both the true and false and then select the appropriate one whereas case statements will only execute one or the other.
Interesting. Thanks.

Quote:
But at this level for toggle on a button on a joystick, we are in the weeds. Write what is readable.
I agree 100%. My questions here are purely academic.


Reply With Quote
  #13   Spotlight this post!  
Unread 17-02-2013, 18:44
Greg McKaskle Greg McKaskle is offline
Registered User
FRC #2468 (Team NI & Appreciate)
 
Join Date: Apr 2008
Rookie Year: 2008
Location: Austin, TX
Posts: 4,752
Greg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond repute
Re: logic gates question

The > was a bit faster than the logic. This is again only on testing on intel and it was about 20% different.

Greg McKaskle
Reply With Quote
Reply


Thread Tools
Display Modes Rate This Thread
Rate This Thread:

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

vB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Forum Jump


All times are GMT -5. The time now is 22:56.

The Chief Delphi Forums are sponsored by Innovation First International, Inc.


Powered by vBulletin® Version 3.6.4
Copyright ©2000 - 2017, Jelsoft Enterprises Ltd.
Copyright © Chief Delphi