Encoder rate noise

[Aren Siekmeier]

Originally Posted by Joe Ross

1x decoding helps reduce noise beyond just reducing counts to within the limit of the FPGA. It also allows additional digital samples between each count, effectively acting like averaging 4 samples at 4x. It also ignores manufacturing tolerances between the different signals, like Ether mentioned. For the S4 encoder, B lags A by 90 degress +/- 60 degrees (max).

What if the FPGA cannot keep up with all of the counts it would be averaging at 1x? Does it still properly count every 4th tick, even though the 3 in between go by too quickly? And then adds in the extra samples (and direction sensing) provided 3 intermediate ticks, provided they are slow enough to capture? Sort of nitpicking...