Encoder rate noise

[Ether]

Originally Posted by Joe Hershberger

For the cRIO, that means if A and B channels both change within a single 6.525 us sampling period on the DIO module, that the count will fail.

...because you can't tell which edge came first, so you don't know the direction.

Of course if you are running anywhere near the digital I/O sampling rate, then the FPGA's built-in rate calculations are so noisy that they are practically useless.

Unless you setup the FPGA to do averaging over a large enough sample size?

You can very accurately get the counts in a fixed time period by using the DMA feature of the FPGA to send the encoder count value at exact intervals measured by the FPGA.

Are there code examples how to do this in all 3 supported languages?