Max Digital IO signal rate

[Knufire]

Originally Posted by joelg236

I don't have much to add for experimental results (most I've pushed is about 120hz), but I question any design that would rely on anything remotely close to the limit of the RIO. Is this more of an educational question or a crazy-design question?

At least on the cRio, you had to be mindful of the resolution of the encoder you put on a flywheel.

[feverittm]

This was not an idle question. While I am not considering running anywhere close to the limit, I also wanted to see how the max frequency compared to the max signal rate from our sensors. I was looking for what people have seen in the past.

[Ether]

Back in late November of 2014 I heard the FPGA DIO sampling frequency was going to be bumped up from ~153KHz (2014 Season) to ~1MHz (2015 Season).

Can anyone confirm that this happened?