SPI Write Limitation

[Peter Johnson]

Originally Posted by gerthworm

Seems like it. The bit of research I've done on this seems to indicate SPI is implemented on the FPGA, which I assume means any buffers are of fixed length. What those lengths are, however, I'm not really sure....

Yes, it's a hardware limitation. Per the Zynq documentation [1], the SPI read and write FIFOs are 128 bytes deep. This matches the behavior you're seeing. Conceptually, functionality could be added to wpilib to do the outer loop for longer writes, but I think this case is rare enough (and there's multiple ways to do it, e.g. use interrupts to determine when to continue filling the FIFO, or periodically check), that it's better left to the user code to implement.

[1] http://www.xilinx.com/support/docume...q-7000-TRM.pdf, section 17.2.4.