Standard Motor Driver Schematic for FRC

[philso]

Originally Posted by Andrew Schreiber

How many of those issues are particular to high current designs? Does something sitting in the 15A constant 30A burst range have to worry quite as much about these issues?

It is the interaction of the circuit inductance AND the rate of change of the current that provokes issues (dV = L * dI/dt). Higher currents typically lead to higher values of dI/dT.

At work, I am working on improving a switching power supply where the peak primary current is less than 1 Amp. The person who originally did the PCB layout clearly didn't know how to do it properly. Neither did the person who designed the transformer. The circuit sprays copious amounts of electrical noise.

If one does not have a thorough understanding of how to control the parasitic inductances inherent in the physical construction of a fast-switching circuit, one WILL have trouble with issues such as noise and over/under-shoot. The parasitic elements are not indicated on a typical schematic since they are dependent on exactly how a circuit is physically implemented. It is up to the designer to determine where in the circuit the parasitic elements will be significant and how they can be mitigated. It is not black magic but it takes many years of hands-on experience to be able to do this effectively. Reading a book, attending a class and being smart are not enough.