Why the sudden burst of code postings?

[Thad House]

Originally Posted by Jared Russell

This caught my eye because we also wrote our own ADXRS453 class last season. Ours was almost entirely a copy of the wpilib ADXRS450 driver, with a couple minor tweaks: https://github.com/Team254/FRC-2016-...S453_Gyro.java

Note that your implementation for the ADXRS453 does rate integration in software at 120Hz based on a Notifier callback. The wpilib implementation does rate integration in an FPGA accumulator at 1KHz.

Your method is certainly adequate for FRC use (and it's all we could do before the cRIO era), but it isn't correct to say that it is more accurate than wpilib's implementation.

For the ADXRS453, its actually not a FPGA accumulator. Its a HAL level notifier running at 200Hz. It was originally at the Java level, but that took about 50% of the CPU if I recall correctly, so it ended up being built at the HAL level.

However I will agree that the wpilib implementation is still probably more accurate. When a notifier comes from the FPGA, it actually pings a Java thread, which then enters Java. So there where always be a context switch whenever entering the Java code. This was another reason the code was done at the HAL level in WPILib. (Note there are some issues with both SPI and Notifiers not being RT threads, that will probably be fixed for 2018, as it was discovered too late and determined to not be critical enough to fix for 2017. However we have some graphs that show that the timers hit pretty much at 5ms every single time with very few misses.)