Offloading intterupts to a counter

[Max Lobovsky]

terminal count? Is this in reference to using an external counter? I know i don't need an interrupt for one, i was talking about using the RC to do the encoder counting. If a terminal count is the last one before counter overflow, than i dont think that's a problem either because i was planning on using a 24 bit counter and i highly doubt the robot will drive that far before reset....

I'm almost sure that the RC doesnt have any sort of built in counter that would allow up/down counting.
It is 40 mhz but from what i have heard, 10k counts is pushing it. I also will be having a user code loop that will be pretty significant, im not solely doing counting.

[KenWittlief]

10kHz is pushing it if each count causes an interrupt - if the internal counters are on an I/O pin then it can count at 10Mhz with a 40MHz clock on the uP

terminal count is when you preload the counter everytime it overflows - so with an 8 bit counter you can have it overflow everytime it counts to 1, or to 256 and everything in between, depending on what you set it up to preload with.

[Max Lobovsky]

I just spent some time looking at data sheet on the 18fxx20 chip that the RC uses. There are 5 counters that i think i can use (as long as their inputs are in fact one of the digital inputs, i think im gonna need to ask IFI about this) there are 3 that can be used as 16 bit and 2 that can only go up to 8 bit. Because i don't see anyway of counting down, the only option is two have two counter's per wheel and use an encoder enterpreter chip that can output two streams, one for up clicks and one for down clicks. This means that at best, i can have one encoder on two 16 bit counters, one on two 8 bit counters, and the other two on interrupts. I think this maybe pointless anyway because the interrupt digital I/O pins and the counter pins are most likely the same (again, i have to ask IFI).

[Joe Johnson]

I want to say right away that I am not a EE (though I sometimes play one on TV ;-).

If you want specific chips, I have found the following from Digi-key. I believe they will work, but it is possible you may need an inverter here or a NOR gate there to get things to work exactly as you want.

As to the 8 bit up/down counter:
SN74ALS867ADW


http://focus.ti.com/lit/ds/sdas115c/sdas115c.pdf

As to an 8 bit parallel load shift register:
74F676

http://www.fairchildsemi.com/ds/74/74F676.pdf

You can have the clock for the counter be driven by one channel of the encoder, the other channel of the encoder is tied to the up/dn pin of the counter.

The CPU drives the "parallel load" mode of the shift register and then shift in the bits to the its input pins.

You can daisy chain the 676's to have the data look like one long register.

You can also cascade the counters if you need to have more counts than an 8 bit number can hold.

Alternatively, you can also reset the counters after you read them so that you can just accumulate the total count inside your CPU. You run the risk potential of missing a count when you reset the counters if you are not careful, but depending on your application, this may or may not be a big deal. With some clever circuitry and/or software you can avoid this problem but this is more than I want to get into here.


I don't know if this helps, but it should be a good start.

Joe J.

P.S. I have used the 676 before so I can vouch for it with first hand knowledge. However, I have not used the 867 before -- I have always had some other 4 bit counters hanging around the office that I could cascaded into whatever size counter I needed. From what you are talking about, I suppose you will need more than 8 bits perhaps 16 bits. This gets tedious with 4 bit counters so I suggested an 8 bit version. Looking at the data sheets though I am pretty sure that it will work out for your application -- perhaps others have favorites they are used to using that they can vouch for from personal experience.

[Max Lobovsky]

Originally Posted by Joe Johnson

I want to say right away that I am not a EE (though I sometimes play one on TV ;-).

If you want specific chips, I have found the following from Digi-key. I believe they will work, but it is possible you may need an inverter here or a NOR gate there to get things to work exactly as you want.

As to the 8 bit up/down counter:
SN74ALS867ADW


http://focus.ti.com/lit/ds/sdas115c/sdas115c.pdf

As to an 8 bit parallel load shift register:
74F676

http://www.fairchildsemi.com/ds/74/74F676.pdf

You can have the clock for the counter be driven by one channel of the encoder, the other channel of the encoder is tied to the up/dn pin of the counter.

The CPU drives the "parallel load" mode of the shift register and then shift in the bits to the its input pins.

You can daisy chain the 676's to have the data look like one long register.

You can also cascade the counters if you need to have more counts than an 8 bit number can hold.

Alternatively, you can also reset the counters after you read them so that you can just accumulate the total count inside your CPU. You run the risk potential of missing a count when you reset the counters if you are not careful, but depending on your application, this may or may not be a big deal. With some clever circuitry and/or software you can avoid this problem but this is more than I want to get into here.


I don't know if this helps, but it should be a good start.

Joe J.

P.S. I have used the 676 before so I can vouch for it with first hand knowledge. However, I have not used the 867 before -- I have always had some other 4 bit counters hanging around the office that I could cascaded into whatever size counter I needed. From what you are talking about, I suppose you will need more than 8 bits perhaps 16 bits. This gets tedious with 4 bit counters so I suggested an 8 bit version. Looking at the data sheets though I am pretty sure that it will work out for your application -- perhaps others have favorites they are used to using that they can vouch for from personal experience.

So basically, the parrallel outputs of the counter are connected to the parrallel inputs of the shift register. The shift register is put permanantly into parallel load mode (Mode is high) Then, to read the shift register, the CPU has a digital IO pin connected to the CP (clock pulse) pin which it pulses, then checks serial output, and repeats to get all 8/16 bits of the counter? I'm not sure if the proper way to do this is to actually have a common clock or something like that, but this seems to be correct, too.

I wrote up some code to do what i think you're saying:

 
char encVel()
{ 
char encVel;
for(int i = 1; i<9; i++)
{
/*set clock to shift register high*/
shiftClkA = 1;
/*read the current bit of the shift register encVel*/
encVel |= serialInput<<i
 
/*set clock back*/
shiftClkA=0;
 
}
/*reset counter*/
counterResetA = 1;
counterResetA = 0;
return encVel;
}