AndyMark SuperShifter Encoders

[Phalanx]

Originally Posted by Abrakadabra

They have a rate of 250 cycles per revolution, or because they're quad encoders, 1000 pulses (interrupts?) per revolution.

Everything I've read says that this interrupt rate is pushing the upper limits of the RC, especially if you are using multiple encoders (we're planning to use two). The trick is that since they are mounted to the final output drive shaft, there is no opportunity to reduce this rate. On the other hand, knowing that AndyMark always optimally engineers their products for use in FIRST competitions, I would think that they picked this particular encoder for a reason.

Should I be concerned? Do I need to look into some kind of divider card as well?

Thanks for any info.

The answer is it depends on which implementation for counting and for interrupt handling you plan to use.

If you use and follow the methods by this white paper:
http://www.chiefdelphi.com/media/papers/1490
(we've done this in the past for lower count encoders ex.. H1-50 from USDigital)

Then yes your are going to be "pushing" the limits" and a line/signal divider might be wise. That is because your code will be interrupting on both the rising and falling edges of both the "A" and "B" phase, so you will get 1024 interrupts per revolution per encoder, yielding 2048 interrupts for two encoders per a single revolution.

If you use "Kevin Watson's" encoder code, the caveat is (as I understand it) that if the encoder is spinning at a high enough rate of speed it is possible for his routines to incorrectly interpret the direction and thereby mis count. (See his FAQ). Which is why we don't use it. But this method will give you only 256 interrupts per revolution and under those conditions there shouldn't be any issue. 512 is significantly lower than 2048.


I do hope this helps.