NEW 2009 Control System Released

[AustinSchuh]

Originally Posted by Tom Line

I admit to not being familiar with the acronyms you are using. VHDL? etc.

http://en.wikipedia.org/wiki/VHSIC_H...ption_Language

Depending on the rules, teams will either rarely touch the FPGA code, or never touch it. So the long compile times for compiling the VDHL code for the FPGA aren't an issue. Most likely FIRST will implement the disable logic in the FPGA. If that is the case, they won't want us to potentially mess up the disable code and therefore won't let us change it.

Most, if not all, development for our robots will be done for the 400 MHz processor. Which should have a quick compile process and a smokin' fast download.