DO write speed

[kamocat]

Okay, I got something about 10 times as fast.
It was locked, else I might have dug deeper. (though I suspect this may be as far as the processor goes)
I have some questions about *why* it is done this way.
It looks like it actually updates all 14 GPIO at the same time. Is this how the module is normally accessed? I ran the channel mapping VI on my computer, and found that the bit placement directly corresponds to the channel number on the DIO module.
What separates these updates from the PWM and relay updates? Is this just an efficient way of passing the data to the Digital Module?

Would it be faster sending a string of data through I2C?

[daltore]

Originally Posted by kamocat

It looks like it actually updates all 14 GPIO at the same time. Is this how the module is normally accessed?

First of all, nice job on speeding it up, it's not always easy. But this is how it's usually done on microcontrollers, I'm not sure if it's the same way on the FPGA. But at least in micros, values are updated an entire register at a time, and it does not impact speed. Basically, the microcontroller is designed in such a way that it tells the port register what ALL of its values are in parallel (for speed), and it updates all 8 pins on the register almost simultaneously.

This is mainly for parallel communication, where you need to update all of the bits in the byte you're trying to send at the same time so you can tell the receiving end of the line when it can look for the new data. It's kind of just a precedent, and they've probably put that into the update protocols of the digital module itself (cRIO communicates to the digital module over a serial connection, that VGA-sized port at the bottom, so all data extraction is done inside the module).

This is all just inferences from working with other microcontrollers, and I know that the cRIO is a completely different animal, but the precedents probably still stand. I'm going to guess that the GPIO bank is made up of two registers coming off of the chip inside the digital module, which would kind of act like a "middle-man". If anyone here knows the actual construction of the cRIO modules, I would love to hear about it.

[EricVanWyk]

Its not just for parallel communication. It is a side effect of the fact that figuring out what to do is often harder than doing it. In designing a microprocessor, it is just as easy to have it update N* pins as it is to only update one. You might as well take advantage.

For serial devices like the cRIO module, it is often quicker to update them all so you don't have to do any addressing. For example, the relay pins on the DSC do just this. We send a reset signal and then clock every single pin out every time. The whole process takes on the order of N+4 clock cycles. If we were to do individual pin addressing, we'd have to clock out the address and then the pin value, which would be on the order of log2(N)+5 per pin. This would be quicker for one or two pins, but loses in a hurry if we are updating many pins.

Note that CAN is taking the opposite strategy: Since there are so many more registers to talk to, the overhead of addressing what you are talking to is worthwhile.


* If N is equal to or less than the width of the processor