Go to Post That sound you hear is of every programmer in the country cringing at the thought. - Billfred [more]
Home
Go Back   Chief Delphi > Technical > Control System > FRC Control System
CD-Media   CD-Spy  
portal register members calendar search Today's Posts Mark Forums Read FAQ rules

 
Reply
Thread Tools Rate Thread Display Modes
  #1   Spotlight this post!  
Unread 21-12-2009, 22:14
ayeckley's Avatar
ayeckley ayeckley is offline
Registered User
AKA: Alex Yeckley
FRC #2252 (Mavericks)
Team Role: Mentor
 
Join Date: Apr 2007
Rookie Year: 2007
Location: Sandusky, OH
Posts: 268
ayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond repute
Latest FPGA code?

I'm having some issues with the 4X encoder setting. At one point circa February 09 (after the release of update 3a) there was a known bug in the FPGA code related to the 4X setting. Even after searching through CD, NI Communities, etc. I haven't been able to figure out if a fix was ever implemented.

Can anyone (Greg?) confirm that FPGA 1.0.0 (which appears to be the image that accompanies the FRC_2009_v11.zip update, which itself part of the FRC Update 3a package) is really the latest image available? It seems that if a fix was ever implemented, the rev should have been bumped. Hence my wondering.

According to the FRC_ImageVersion.txt file on the cRIO, I've got:

Image: FRC_2009_v11.zip
Date: 1/23/2009
NetComm: 1712
FPGA: 1.0.0

Thanks in advance...
__________________

Reply With Quote
  #2   Spotlight this post!  
Unread 23-12-2009, 09:39
Greg McKaskle Greg McKaskle is offline
Registered User
FRC #2468 (Team NI & Appreciate)
 
Join Date: Apr 2008
Rookie Year: 2008
Location: Austin, TX
Posts: 4,752
Greg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond repute
Re: Latest FPGA code?

I'm actually not the definitive guy for this. I believe this has been truly fixed for this year, and the workaround last year was to turn on a bit of averaging.

I cannot say for sure if it was fixed last year, or if the workaround was the solution.

Greg McKaskle
Reply With Quote
  #3   Spotlight this post!  
Unread 23-12-2009, 10:24
ayeckley's Avatar
ayeckley ayeckley is offline
Registered User
AKA: Alex Yeckley
FRC #2252 (Mavericks)
Team Role: Mentor
 
Join Date: Apr 2007
Rookie Year: 2007
Location: Sandusky, OH
Posts: 268
ayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond repute
Re: Latest FPGA code?

Thanks Greg. I'll continue to use the workaround until Kickoff '10, and then use the new version after that. Now if I could only figure out why the Global that stores the rate from "Encoder Get" keeps getting zeroed out then I'd have this thing licked...
__________________

Reply With Quote
  #4   Spotlight this post!  
Unread 23-12-2009, 10:36
Greg McKaskle Greg McKaskle is offline
Registered User
FRC #2468 (Team NI & Appreciate)
 
Join Date: Apr 2008
Rookie Year: 2008
Location: Austin, TX
Posts: 4,752
Greg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond repute
Re: Latest FPGA code?

You may already know this, but right click on the global and select Find>>References. It will bring up a list of the readers and writers. You can click or hit ctl-g to go from one to the next and think about how the writers may be interacting. Ideally, you will only have one writer, but if you need to update in more than one location, at first glance that seems impossible.

You may want to read up on functional globals in LV. Each non-reentrant subVI automatically acts as a critical section, ensuring that only one caller is active in the function at a time. This allows you to put data modifications within a common function to ensure that your parallel updates are playing nicely.

The single update also makes it easier to put traps into your code to break when the update value is zero. Feel free to ask more questions.

Greg McKaskle
Reply With Quote
  #5   Spotlight this post!  
Unread 23-12-2009, 23:40
ayeckley's Avatar
ayeckley ayeckley is offline
Registered User
AKA: Alex Yeckley
FRC #2252 (Mavericks)
Team Role: Mentor
 
Join Date: Apr 2007
Rookie Year: 2007
Location: Sandusky, OH
Posts: 268
ayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond reputeayeckley has a reputation beyond repute
Re: Latest FPGA code?

Well, I've got my Global Variable issue ironed out now.

I did read the available docs carefully but found that I wasn't really off-base in my understanding of how they work in LabVIEW. Although that boosted my ego a bit, it didn't help me figure out the problem. My next step was to methodically go through the main VI data flow in full detail, and I eventually realized my mistake during that process.

The architecture I'm experimenting with deliberately writes to the same Global in multiple locations within different SubVIs. The states within this architecture are structured so that only one Global write operation is active at any given time. Or so I thought. It turns out that I'd placed a Global write operation on the exterior of a set of cases (Init, Execute, Stop in Disabled.VI), when I really should have put it only withinin the Stop case. The unintentional, repeating write was trodding all over the intentional one (in Periodic Tasks.VI ) with its stale data.

So, as expected: user error.
__________________

Reply With Quote
  #6   Spotlight this post!  
Unread 24-12-2009, 10:09
Greg McKaskle Greg McKaskle is offline
Registered User
FRC #2468 (Team NI & Appreciate)
 
Join Date: Apr 2008
Rookie Year: 2008
Location: Austin, TX
Posts: 4,752
Greg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond reputeGreg McKaskle has a reputation beyond repute
Re: Latest FPGA code?

Sounds like you are on your way.

Be sure to watch for read/modify/write sequences that may overlap. If you are building your data access around the communications protocol state machine, you should be in pretty good shape. You may still find it useful to push the global accesses down into a subVI and add a check-out and check-in mechanism. You can put a counter inside the subVI that allows you to put validation code to catch any unexpected accesses in the future and put up a dialog or hit a breakpoint. This is especially useful if someone else will work on the code.

Greg McKaskle
Reply With Quote
  #7   Spotlight this post!  
Unread 10-01-2010, 19:03
jhersh jhersh is offline
National Instruments
AKA: Joe Hershberger
FRC #2468 (Appreciate)
Team Role: Mentor
 
Join Date: May 2008
Rookie Year: 1997
Location: Austin, TX
Posts: 1,006
jhersh has a reputation beyond reputejhersh has a reputation beyond reputejhersh has a reputation beyond reputejhersh has a reputation beyond reputejhersh has a reputation beyond reputejhersh has a reputation beyond reputejhersh has a reputation beyond reputejhersh has a reputation beyond reputejhersh has a reputation beyond reputejhersh has a reputation beyond reputejhersh has a reputation beyond repute
Re: Latest FPGA code?

Quote:
Originally Posted by ayeckley View Post
I'm having some issues with the 4X encoder setting. At one point circa February 09 (after the release of update 3a) there was a known bug in the FPGA code related to the 4X setting. Even after searching through CD, NI Communities, etc. I haven't been able to figure out if a fix was ever implemented.

Can anyone (Greg?) confirm that FPGA 1.0.0 (which appears to be the image that accompanies the FRC_2009_v11.zip update, which itself part of the FRC Update 3a package) is really the latest image available? It seems that if a fix was ever implemented, the rev should have been bumped. Hence my wondering.

According to the FRC_ImageVersion.txt file on the cRIO, I've got:

Image: FRC_2009_v11.zip
Date: 1/23/2009
NetComm: 1712
FPGA: 1.0.0

Thanks in advance...
The image you were using did not include the fix in the FPGA. There was a workaround in WPILib that would adjust for the bug.

In the image for this year, the bug is fixed in the FPGA. Look for version 2010 and revision 1.3.0 of the FPGA. The corresponding workarounds in the library are also removed for 2010.

You can look here for a list of changes since 2009. It's still in progress, but the FPGA changes are all there.

Cheers!
-Joe
Reply With Quote
  #8   Spotlight this post!  
Unread 10-02-2010, 23:30
plusk01 plusk01 is offline
Registered User
AKA: Parker Lusk
FRC #1742 (Shockwave)
Team Role: Programmer
 
Join Date: Dec 2009
Rookie Year: 2009
Location: Oklahoma
Posts: 3
plusk01 is an unknown quantity at this point
Re: Latest FPGA code?

This problem I'm having may or may not be related, but here it is:

I started programming with encoders (the US Digital shaft encoder) in LabVIEW and every once in a while when front panel debugging, I'll get an error when trying to run Robot Main on the cRIO with my Encoder code. I get the same error with the pre-written encoder examples. I posted in this thread because the 4x encoder setting and FPGA were mentioned.

The error I get when I try to Run my LabVIEW code on my robot is that it fails to deploy the NI_FPGA_Interface.lvlib:CounterEncoderSourceConver tion.lvlib and then the entire deployment process fails.

I believe it is a problem with the supplied Encoder libraries, because this error didn't come up until I started opening encoders.

Anyone else experience the same problem?


Parker Lusk
Programming
Shockwave Team 1742
Reply With Quote
  #9   Spotlight this post!  
Unread 11-02-2010, 10:55
Alan Anderson's Avatar
Alan Anderson Alan Anderson is offline
Software Architect
FRC #0045 (TechnoKats)
Team Role: Mentor
 
Join Date: Feb 2004
Rookie Year: 2004
Location: Kokomo, Indiana
Posts: 9,113
Alan Anderson has a reputation beyond reputeAlan Anderson has a reputation beyond reputeAlan Anderson has a reputation beyond reputeAlan Anderson has a reputation beyond reputeAlan Anderson has a reputation beyond reputeAlan Anderson has a reputation beyond reputeAlan Anderson has a reputation beyond reputeAlan Anderson has a reputation beyond reputeAlan Anderson has a reputation beyond reputeAlan Anderson has a reputation beyond reputeAlan Anderson has a reputation beyond repute
Re: Latest FPGA code?

Quote:
Originally Posted by plusk01 View Post
The error I get when I try to Run my LabVIEW code on my robot is that it fails to deploy the NI_FPGA_Interface.lvlib:CounterEncoderSourceConver tion.lvlib and then the entire deployment process fails.

I believe it is a problem with the supplied Encoder libraries, because this error didn't come up until I started opening encoders.

Anyone else experience the same problem?
At least two teams have posted about this issue. When we had it happen to us, the thing that finally made the problem go away was reimaging the cRIO.

See http://www.chiefdelphi.com/forums/sh...ad.php?t=81366 for discusson.
Reply With Quote
  #10   Spotlight this post!  
Unread 22-02-2010, 13:15
PICgnosis's Avatar
PICgnosis PICgnosis is offline
Registered User
AKA: Karen Suhm
FRC #0842 (Falcon Robotics)
Team Role: Mentor
 
Join Date: Jan 2006
Rookie Year: 2003
Location: Phoenix, AZ
Posts: 45
PICgnosis is on a distinguished road
Re: Latest FPGA code?

Quote:
Originally Posted by Alan Anderson View Post
At least two teams have posted about this issue. When we had it happen to us, the thing that finally made the problem go away was reimaging the cRIO.

See http://www.chiefdelphi.com/forums/sh...ad.php?t=81366 for discusson.
Make that three teams. Reimaging the cRIO resolved the issue for us as well.
Reply With Quote
Reply


Thread Tools
Display Modes Rate This Thread
Rate This Thread:

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

vB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Forum Jump

Similar Threads
Thread Thread Starter Forum Replies Last Post
bb's latest johnr General Forum 4 25-11-2009 14:02
FPGA Image idahorobot FRC Control System 1 12-02-2009 01:23
What is max sample rate of the FPGA? Bryscus FRC Control System 3 26-01-2009 14:17
latest FRC code - undefinded variables RedOctober45 Programming 1 09-01-2008 09:50
FPGA getting started Rickertsen2 Electrical 4 10-09-2005 12:52


All times are GMT -5. The time now is 16:45.

The Chief Delphi Forums are sponsored by Innovation First International, Inc.


Powered by vBulletin® Version 3.6.4
Copyright ©2000 - 2017, Jelsoft Enterprises Ltd.
Copyright © Chief Delphi