Speed Controller Design

[Ether]

I have a bunch of comments and questions. TIA to anyone who has the patience to read them all and shed some light :-)

quote (1)

Al Skierkiewicz, Post 22:

in the Jaguar, only the high side FET is PWM while the low side FET is ON for direction.

Would this only be for the tan Jag, not the black? see quote (4)

quote (2)

Al Skierkiewicz, Post 22:

The Brake Mode will turn on both low side FET pairs in a zero throttle condition

In earlier posts, it was stated that for locked antiphase there would be a 50% fwd/rev duty cycle for a zero command. This would seem to preclude turning on both low-side FETs simultaneously unless there were special logic to override the locked antiphase for the zero-throttle condition. Perhaps you are referring to the tan Jags only?

quote (3)

Al Skierkiewicz, Post 22:

The locked anti-phase that Eric refers to is a condition where the controller is supplying a 50% duty cycle of forward and reverse commands... Please note that this could be a relatively large current demand as current is flowing in the motor all the time.

The current in the motor under this condition should be very nearly zero. The current never has a chance to rise to appreciable levels since the voltage is changing directions so fast. The motor inductance is the key here.

quote (4)

Gdeaver, Post 19:

Black jags switch different than tan jags. The tan jags are high side switchers. The black jags are locked antiphase. Allegro makes a nice fet full bridge automotive driver chip. The A3941K. The data sheet gives a good description of the different ways the Fet bridge can be driven. May be it will help.

"Black jags switch different than tan jags. The tan jags are high side switchers. The black jags are locked antiphase."

I'm not disputing what you said, but could you please provide a link to this information?

"Allegro makes a nice fet full bridge automotive driver chip. The A3941K. The data sheet gives a good description of the different ways the Fet bridge can be driven."

Are you saying that the Black Jags use the Allegro A3941K instead of the Fairchild FAN5109?

quote (5)

Geek 2.0, Post 17:

That only makes too much sense, thanks. Where would you possibly draw the line for what works with locked antiphase?

It would depend on the motor inductance. Very low motor inductance would require a higher switching frequency. Very high motor inductance would allow a lower switching frequency.

quote (6)

Geek 2.0, Post 15:

Okay, for the sake of education (and that I've exhausted the extent of Wikipedia's ability to have a page on every minuscule topic) could someone please give a better definition of locked antiphase? I understand that it's using a PWM where a 50% duty cycle is brake, 100% is full forward, 75% half, 25% half reverse, etc. But maybe an illustration or something to that effect?

I think what you described in quote (10) below would be locked antiphase.

quote (7)

Geek 2.0, Post 8:

It just seems odd that it's running forward 75% of the time and backwards 25% of the time to go forward at 50%... wouldn't it make more sense to just go forward 50% of the time?

I believe EricVanWyck stated in post 11 that locked antiphase gives better fine speed control at low speeds. I'm not entirely sure why this is, perhaps Eric or someone else could elaborate.

quote (8)

kamocat, Post 5:

On the Jaguar (unlike the Victor) the H-bridge switches between 12v and 0v, not 12v and "open".

Could you clarify what you meant by this? And how does it apply to locked antiphase, and coast mode?

quote (9)

Geek 2.0, Post 1:

After carefully studying the datasheet http://media.digikey.com/pdf/Data%20...client_id=5042 for the MOSFET driver, I learned that if the signal coming into PWM is high, HDRV is high (opening the MOSFETs it controls) and LDRV is low (closing the MOSFETs it controls).

Is the FAN5109 used only in the tan Jag, or in the black as well?

quote (10)

Geek 2.0, Post 1:

If the PWM square waves are inverse of each other (or any other alignment), when one is high and the other is low, current will flow (e.g. when the left side is high and the right is low, current will flow from Q1 to Q4). However, since the wave then inverts, it would then switch which MOSFETs are open, thus switching the motor direction...

Is this how the black Jag does locked antiphase, or does it use the Allegro driver?

quote (11)

Geek 2.0, Post 1:

There is one other possibility still: What if they aren't putting a PWM input into the PWM pin, but rather the OD (Output Disable) and a HIGH or LOW into PWM, depending on motor direction?

OD pulls both HDRV and LDRV low (closing their MOSFETs) if it is low.

http://img.skitch.com/20100831-dgeux...3h7cmd5ece.jpg

When PWM is HIGH on the left side, then Q1 is open and Q3 is closed. If it is LOW, Q1 is closed and Q3 is open. The same goes for the other side. Then the PWM into OD would close whichever is open when it is low.

Does the Jag firmware ever drive the FAN5109 this way?

quote (12)

Geek 2.0, Post 1:

Jaguar Schematic Rev B.pdf (56.0 KB)
http://www.chiefdelphi.com/forums/at...6&d=1283287949

Is this the schematic for the Black Jag, or the Tan Jag, or both ?

[Geek 2.0]

Yeah, I kind of noticed that this thread has a lot of contradictory information, so clarification like this is nice. I'll try and clarify on what I said.

Originally Posted by Ether

Is the FAN5109 used only in the tan Jag, or in the black as well?

I wouldn't be able to tell you, because there is no schematic posted for the tan Jags.

Originally Posted by Ether

Is this how the black Jag does locked antiphase, or does it use the Allegro driver?

As far as I understand, that's how the tan Jag does locked antiphase.

Originally Posted by Ether

Does the Jag firmware ever drive the FAN5109 this way?

I don't have the Jag firmware. Anyone have it?

Originally Posted by Ether

Is this the schematic for the Black Jag, or the Tan Jag, or both ?

Tan Jaguar, because like I said earlier, the Black Jaguar doesn't have a posted schematic.


Maybe we should make a white paper on this subject, for clarity.

[EricVanWyk]

Both versions of the Jaguar are sold as Reference Design Kits - all of their information can be found online. Every last detail can be found, provided you are willing to digg.

http://www.luminarymicro.com/products/rdk_bdc.html
http://www.luminarymicro.com/products/rdk-bdc24.html

[Ether]

Originally Posted by EricVanWyk

Both versions of the Jaguar are sold as Reference Design Kits - all of their information can be found online. Every last detail can be found, provided you are willing to digg.

http://www.luminarymicro.com/products/rdk_bdc.html
http://www.luminarymicro.com/products/rdk-bdc24.html

I am willing to dig, I was just digging in the wrong places :-)

Thanks for the links.

[Geek 2.0]

Yeah, thanks! I couldn't find the Black Jaguar info for the life of me!

This might provide a spec of clarification

[Ether]

I see the Black Jag uses the A4940 to drive the FETs.

http://www.allegromicro.com/en/Produ.../4940/4940.pdf

I'm still wondering if the tan jag drives the FAN5109's in non-locked-antiphase the way Geek 2.0 described in the original post. It sure looks that way, with the PWMA & PWMB going to the Output Disable in the FAN5109. I haven't checked to see if the firmware source code is in the info I downloaded, and even if it is, not sure I could decipher it.

[Geek 2.0]

I was just going to comment on the Allegro driver in the black Jaguars. If I do end up designing my "own" speed controller, I'll probably end up using an Allegro driver.

Note also that the main difference between the A4940 (in the black jaguar) and the A3941 (described earlier) is that the A3941 has a 5V regulated output on it, whereas the A4940 does not.

[Al Skierkiewicz]

Ether,
The switching of the FETs was explained to me by a member of the Luminary team at the end of 2009. I have no documentation that either of the Jags are locked anti-phase devices in normal control although it is my understanding that all controllers are capable of this action. There is no mention of locked anti-phase in either of the manuals for Jags. The brake mode on both Jags is described in the literature as acting the same, a simple dynamic short across the motor with both low side FETs turned ON. In the description for both Jags, there is a caveat that while this mode does provide braking at zero speed it should not be considered a hard brake that prevents movement.
While there is minimal current if the duty cycle is low in locked anti-phase, a condition where the duty cycle is 50% (common use), even in the Jag the current has a chance to rise to near full level due to the inductance of the motor.
As I said in an earlier post, the Fairchild device is reportedly out of production. This had a lot to do with the change in FET drivers in addition to the decision to move to 24 volts.

Geek,
PWM signals are used in two ways in the speed controllers. The input PWM for hobby interface is a defined standard that is used to send control signals to servos and speed controllers for both direction and speed. The output of the speed controllers is also PWM but in no way is it similar to the input signal. For the motor side, 50% duty cycle means the motor is supplied current for 50% of the time. That is, a 3.3mSec pulse for the Victor or a 33 microSec pulse for the Jags. For direction the output current actually changes polarity.

For all,
It is my understanding that both Jags leave the low side FETs ON during all throttle conditions except zero (subject to which direction pair is selected) and during locked anti-phase (where the direction is changing at a 50% duty cycle rate). I think it has to do with the need for charging of the gate drive bootstrap capacitor. The Victor designers chose to open both FETs during the OFF period. In early designs of the Victor, the switching frequency was 2kHz. Engineers at IFI chose to move to 150Hz to give maximum low throttle torque for the motors we were using at the time. 150Hz is less affected by the inductance of the motors. It does however, give the impression that low speed linearity suffers and it does cause some acoustic output for the motors it is controlling. 15kHz switching does interact with the inductance of the motors and is sufficiently high to cause no discernible acoustic noise except in the smaller motors.

[JesseK]

Originally Posted by Al Skierkiewicz

For all,
It is my understanding that both Jags leave the low side FETs ON during all throttle conditions except zero (subject to which direction pair is selected) and during locked anti-phase (where the direction is changing at a 50% duty cycle rate). I think it has to do with the need for charging of the gate drive bootstrap capacitor. The Victor designers chose to open both FETs during the OFF period. In early designs of the Victor, the switching frequency was 2kHz. Engineers at IFI chose to move to 150Hz to give maximum low throttle torque for the motors we were using at the time. 150Hz is less affected by the inductance of the motors. It does however, give the impression that low speed linearity suffers and it does cause some acoustic output for the motors it is controlling. 15kHz switching does interact with the inductance of the motors and is sufficiently high to cause no discernible acoustic noise except in the smaller motors.

Would this affect the choice of speed controller for a robotic subsystem? For example, would fine PID control on a shoulder joint that needs more low-throttle torque be more efficient with a Victor over a Jag? Or is the difference (mostly) negligible?

[Al Skierkiewicz]

Jesse,
There are pros and cons for both types. In the application you describe, I believe either type will work, but the PID variables will be vastly different between the two types. Whatever non-linearity might be present is capable of being corrected in software. Please be advised that many people have reported that window motors don't play well with Jaguars. I have nothing more at this point in the discussion than that there appears to be a interaction with both the locking pawls internal to the window motors and some interaction with the armature/worm gear interface when using the Jaguars. Some teams reported no problems with this combination. I am still looking for input from teams who have been doing off season testing.

[Ether]

Originally Posted by Al Skierkiewicz

While there is minimal current if the duty cycle is low in locked anti-phase, a condition where the duty cycle is 50% (common use), even in the Jag the current has a chance to rise to near full level due to the inductance of the motor.

In locked anti-phase, when the output duty cycle is low you have HIGH motor current.

When the output duty cycle is 50% you have nearly zero motor current, due to the inductance of the motor.

The output of the speed controllers is also PWM but in no way is it similar to the input signal. For the motor side, 50% duty cycle means the motor is supplied current for 50% of the time.

... except when the output is locked antiphase, in which case 50% output duty cycle means the motor is supplied a positive voltage drop 50% of the time and a negative voltage drop the other 50%, resulting in near-zero motor current (due to the inductance of the motor)

[Al Skierkiewicz]

Ether,
When the locked anti-phase duty cycle is 50% current is flowing 100% of the time. 50% in one direction, 50% in the other, correct? An averaging meter will read this as zero while a true reading RMS will not.
During a previous discussion (2009) someone measured a CIM motor at .12 mH and 90 mOhm. At 150Hz this is very low but at 15kHz it is significant.

[Ether]

Originally Posted by JesseK

would fine PID control on a shoulder joint that needs more low-throttle torque be more efficient with a Victor over a Jag?

No. In any event, if your particular application has a unique need for higher torque gain at low throttle, that is easily done in software.

[Ether]

Originally Posted by Al Skierkiewicz

Ether,
When the locked anti-phase duty cycle is 50% current is flowing 100% of the time. 50% in one direction, 50% in the other, correct?

When the locked anti-phase duty cycle is 50%, voltage drop across the motor is positive 50% of the time and negative 50% of the time. Under these conditions, the motor inductance prevents any significant motor current from developing.

An averaging meter will read this as zero while a true reading RMS will not.

Both average and true RMS will be near-zero. At 15000Hz switching frequency and 50% duty cycle, the voltage drop will stay at each polarity only 33 microseconds. This is short compared to the rise time for the current (due to the motor inductance). Thus even the peak current never amounts to much. So the RMS is also near-zero.

During a previous discussion (2009) someone measured a CIM motor at .12 mH and 90 mOhm. At 150Hz this is very low but at 15kHz it is significant.

The significant inductance of the CIM at 15KHz (Jaguar) is what suppresses the current at 50% motor duty cycle in locked antiphase.

[Al Skierkiewicz]

Ether,
I have realized we were talking about two different concepts. My mistake. I was talking about locked rotor motor control by driving the motor anti-phase signals to hold the output shaft in place. In this method, current is high through the motor.
I am guessing you are talking about the HBridge control. Your statements are correct. It appears that the Jags can produce this kind of control through the CAN interface only. The current Victor controllers cannot. Both controllers produce zero volts across the motor at zero throttle.