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Unread 03-09-2010, 09:51
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Re: Speed Controller Design

Quote:
Originally Posted by Al Skierkiewicz View Post
While there is minimal current if the duty cycle is low in locked anti-phase, a condition where the duty cycle is 50% (common use), even in the Jag the current has a chance to rise to near full level due to the inductance of the motor.

In locked anti-phase, when the output duty cycle is low you have HIGH motor current.

When the output duty cycle is 50% you have nearly zero motor current, due to the inductance of the motor.


Quote:
The output of the speed controllers is also PWM but in no way is it similar to the input signal. For the motor side, 50% duty cycle means the motor is supplied current for 50% of the time.
... except when the output is locked antiphase, in which case 50% output duty cycle means the motor is supplied a positive voltage drop 50% of the time and a negative voltage drop the other 50%, resulting in near-zero motor current (due to the inductance of the motor)


Last edited by Ether : 03-09-2010 at 10:09.
 


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