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Unread 21-11-2010, 11:13
Greg McKaskle Greg McKaskle is offline
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Re: Assembly On The cRIo

The processor instruction set used by the cRIO was called the 603e when I was familiar with it. It is a very basic RISC and predates the Altivec extensions for vector math and such. Any book on PPC will get you going, and IIRC, unless you are disabling interrupts or messing with the MMU, they are quite similar.

As for the FPGA. it is a very different approach. Normal micro-controllers and computer CPUs use their basic circuits to construct a higher-order but flexible Von-Neumann machine that retrieves some memory (an instruction such as add). This activates and deactivates portions of the circuit to carry out the add operation on the contents of other fetched memory or registers. By supporting the most basic operations, the circuits enable a sequence of instructions and initial data to specify a higher level and super-flexible machine that can compute almost anything.

The FPGA circuits, as the name implies, is an array of low-level logic gates and other resources that can be used to build up a micro-controller, ad-hoc micro-controller components, or pretty much any other special-purpose circuit. Traditionally, they were used to prototype, and when the prototype functioned correctly, they would spend the time and money to produce the special purpose ASIC chip -- a silicon level single-purpose device which could operate faster and was cheaper to produce. It was used instead of a micro-controller either due to speed or cost issues.

As capabilities of FPGAs grew, they were not only used for prototypes, but also for HW flexibility. In the nineties, NI started using them on high speed boards to be patched to resolve bus control issues between platforms or between OSes or OS versions.

cRIO stands for "compact, Reconfigurable, Input and Output". The R represents the FPGA's ability to construct highly flexible custom circuits that allow the customer to design their own high speed circuit as part of their monitoring or control application. One day, they can route digital values from a prototype communications board and monitor for circuit glitches. The next day, the same HW has a new FPGA image that produces the signals for an automotive ECU. The following day, it might be used to synchronize clocks on various cards to enable a sensitive measurement within a prototype MRI machine. And on its days off, it can implement the PWM generation, encoders, and accumulators to allow a FIRST robot to be able to do all of those things in parallel with HW timing.

I'd suggest reading about FPGAs as future computing architectures will, I believe, become somewhat more like the RIO, with circuits that reconfigure for special tasks, but aren't limited to the I/O speeds of micros and aren't purpose limited like ASICs. If you have a project and want to program them, you can use Xilinx tools or NI tools to program the cRIO FPGA -- for offseason nonrobotics projects of course.

Greg McKaskle
 


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