Jaguar current sensing technical details?

[Joe Ross]

Marshal, your picture looks like the gray jaguar schematic (10/28/2008), while Ether's looks like the black jaguar's schematic (10/7/2009). Where did you find a November 2010 schematic?

[kamocat]

Oh, oops.
I got it from the RDK-BDC page, not the RDK-BDC24 page.
That would explain it.

I looked at the date again, and it actually said November of 2008. However, the Firmware Development Package is from November of 2010. The Firmware Development Package is probably exactly the same as is on the RDK-BDC24 page

I was wondering why they were using a Fairchild part. I would think TI would avoid that if at all possible.
I'm going to go back and edit my post.

[kamocat]

Two additional sources of error:

Brush commutation on the motor

The current shunt resistor is on the supply end of the H-bridge drivers; it is not subject to the motor impedance, because it is cut off from the motors when the FETs are in the OFF state.
What would the current through this resistor look like over a span of 200 us? (That is, 3 pulses at 15 khz)

[Al Skierkiewicz]

Marshall,
Part of the answer to your questions above, Luminary Micro was not a part of TI when the Jag was under development. The series resistance also affects the max current that the bridge is capable of delivering to the load. Raising the value of the sense resistor opposes the lower "ON" resistance FETs that were chosen for this design.
In the case of the Tan Jags, high current on a CIM (say 100amps) develops a significant amount of power in the sense resistor. It is a 2 watt resistor trying to dissipate 5 watts. In sustained pushing matches, the resistor heats up a lot and in some cases desoldered itself from the board.

[Ether]

Hi Marshal,

A couple of observations and a question:

Two additional sources of error:

Brush commutation on the motor

The Brush resistance is in series with the current sense resistor so it shouldn't cause error in the current sense resistor's reading.

The current shunt resistor is on the supply end of the H-bridge drivers; it is not subject to the motor impedance, because it is cut off from the motors when the FETs are in the OFF state.

It's on the high side in the Black Jag.

In the Tan Jag, it's on the low side.

Either way, the current sense resistor is not in the current path during the OFF portion of the duty cycle. See attached images. For simplicity, I showed path through only one FET of each pair, and only for + currents. Green path is during ON portion. Blue path is during OFF portion (for high-side switching). Red path is during OFF portion (for low-side switching).

I don't know if the Jags use high-side, or low-side, or some other switching method. Does anyone know, definitively, what switching method the Jags use? I've heard many different claims.

What would the current through this resistor look like over a span of 200 us? (That is, 3 pulses at 15 khz)

Good question. I'd like to see some actual data. I did a simulation with the Black Jag with a CIM with locked rotor (no back emf) and included the CIM's resistance and inductance, and included the Zener diode voltage. I'd like to see how it compares to actual data.

[Kevin Sevcik]

From reference design source code, the Tan Jags pulse the high side FETs and leave the low side FETs on during a PWM cycle.

[kamocat]

Originally Posted by Kevin Sevcik

From reference design source code, the Tan Jags pulse the high side FETs and leave the low side FETs on during a PWM cycle.

How does it do that?
Is it modulating the Output Disable pin?

[Kevin Sevcik]

Why yes, yes it is. Don't ask me why, but that's what the code in the tan jag does. They could just as easily modulate the pwm pin, but they don't for some reason. Perhaps the driver doesn't have adequate shoot through protection.

[kamocat]

No, they can't modulate the PWM pin. If they did, that would be locked antiphase, because the MOSFET driver would alternate between driving the low side and driving the high side.

[Kevin Sevcik]

Originally Posted by kamocat

No, they can't modulate the PWM pin. If they did, that would be locked antiphase, because the MOSFET driver would alternate between driving the low side and driving the high side.

Oooookay. Too much crosstalk that's off-topic for this particular thread. I'm officially vetoing any further PWM control discussion in this thread and picking it back up in the Modeling motor control thread. I'll see everyone over there.

[kamocat]

Sure. I'll refocus to the intent of this thread.

Why do you think the Jaguar has so much noise in its current measurement?
This graph from the INA193AID datasheet might help:

With a 0.001 ohm resistor, 1mv input equates to 1A.

[Kevin Sevcik]

Actually, I'd look move to pages 8 and 9 of the data sheet, on "Accuracy variations as a result of Vsense and common mode voltage".

This amp is apparently most accurate at sense voltages >20mv. Which equates to 20A for us. There's 3 operating cases in this range, and we're not in the worst... So it could be worse? I've attached a snapshot of an example graph. What it boils down to is that the amp goes non-linear below 20mv, and eventually lands on some positive offset voltage at the output, instead of zero. They state the worst case zero offset at the output is 300mv. It looks less linear the closer you get to 0 Vsense, so that's exciting too.

Oh yeah. And both Jags record a zero offset for the current ADC on power up, and then subtract that from current readings forever after. So if you end up with the worst case 300mv offset, then your readings above 20A will read 15A low. We're probably not getting this worst-case scenario, but that's obviously going to affect the accuracy of ALL the current readings. Better might be to just assume/hope that you have little absolute error in the ADC, and just use the zero offset as a linear correction below 20mv Vsense.

Maybe FIRST will let us modify the Jag firmware this year?

Yeah, you're right. That's never gonna happen.

[EricVanWyk]

Originally Posted by Kevin Sevcik

Maybe FIRST will let us modify the Jag firmware this year?

Yeah, you're right. That's never gonna happen.

But TI can modify it. Perhaps you could submit the change to them. Bonus points for sending code with the request.

[kamocat]

Originally Posted by Kevin Sevcik

Actually, I'd look move to pages 8 and 9 of the data sheet, on "Accuracy variations as a result of Vsense and common mode voltage".

Where did you find this datasheet? It's certainly not the INA193AID one I attached.

[kamocat]

Originally Posted by Kevin Sevcik

Actually, I'd look move to pages 8 and 9 of the data sheet, on "Accuracy variations as a result of Vsense and common mode voltage".

This amp is apparently most accurate at sense voltages >20mv. Which equates to 20A for us. There's 3 operating cases in this range, and we're not in the worst... So it could be worse? I've attached a snapshot of an example graph. What it boils down to is that the amp goes non-linear below 20mv, and eventually lands on some positive offset voltage at the output, instead of zero. They state the worst case zero offset at the output is 300mv. It looks less linear the closer you get to 0 Vsense, so that's exciting too.

The accuracy of the INA193−INA198 current shunt monitors is a function of two main variables: VSENSE (VIN+ − VIN−) and common-mode voltage, VCM, relative to the supply voltage, VS. VCM is expressed as (VIN+ + VIN−)/2; however, in practice, VCM is seen as the voltage at VIN+ because the voltage drop across VSENSE is usually small.
This section addresses the accuracy of these specific operating regions:

• Normal Case 1: VSENSE ≥ 20mV, VCM ≥ VS
• Normal Case 2: VSENSE ≥ 20mV, VCM < VS
• Low VSENSE Case 1: VSENSE < 20mV, −16V ≤ VCM <0
• Low VSENSE Case 2: VSENSE < 20mV, 0V ≤ VCM ≤ VS
• Low VSENSE Case 3: VSENSE < 20mV, VS < VCM ≤ 80V

So we're in Low VSENSE Case 3, where VCM is greater than the 5v supply voltage? That must be why they measure current on the high side.

Above 20A, then, this current measurement is incredibly accurate; within %0.001 if your battery is at 11.5v or greater.

Originally Posted by Kevin Sevcik

Oh yeah. And both Jags record a zero offset for the current ADC on power up, and then subtract that from current readings forever after. So if you end up with the worst case 300mv offset, then your readings above 20A will read 15A low. We're probably not getting this worst-case scenario, but that's obviously going to affect the accuracy of ALL the current readings. Better might be to just assume/hope that you have little absolute error in the ADC, and just use the zero offset as a linear correction below 20mv Vsense.

Except for that. They just made it measure low for the WHOLE range. So that means, if you get a reading of 5A or greater, you need to add 15A to make it accurate. XP

Wait a minute. Where did you get the 15A? I see 0.3v on the graph, which equates to 30A.