Vex SW Architecture

[yogibear]

I would like to understand the SW architecture that is used on the Vex system. I have found 2 sources of information so far, but I am hoping for more detail. I want to understand any timing constraints so I can write code that can actually executed in the available time. IFI help folks could only suggest that I read the PIC documentation, even though their implementation is what I actually concerned with.

What is actually happening in the background when I have encoders and an ultrasonic range finder that generate interrupts?

I've been told that if I use PrintToScreen statements to check the timing of code, I will actually alter the time to execute. Sound a bit like Heizenberg's Uncertainty to me.

Thanks for any and all help,
Pat

The WPILib documentation says
"The user to master communication happens periodically over a serial bus connecting the two processors. Every 26ms for FRC or 14ms for VEX the master processor sends the current state of the OI to the user processor and receives the current speeds for the PWM outputs to drive the motors. If this communication does not happen, the master processor will stop the user processor resulting in the flashing red code error light."

The following code is found in the default main.c routine, which is not necessarily indicitive of how fast custom user code can run.
if (statusflag.NEW_SPI_DATA) /* 18.5ms loop area */
{ /* I'm slow! I only execute every 18.5ms because */
/* that's how fast the Master uP gives me data. */
Process_Data_From_Master_uP(); /* You edit this in user_routines.c */