I was told that in the FPGA on the old cRIO certain digital ports were optimized for counting purposes (and as such we were limited on how many encoders we could use).
Does the rRIO have a similar restriction (or are all ports able to be used for encoders/counters equally)? I can’t find any documentation of such a limitation (but I couldn’t find it for the cRIO either).
Thanks for any info…
The diagram here suggests than any GPIO would work.
The limit isn’t on the ports, but the number of counter objects to route the ports too.
Is this eight total counters, each of which may be any of the three types (
one pin rise/fall, two pin up/down, or two/three pin quadrature)? This is how the text reads, but the diagram looks more like there are 8 of each.
Also, we’re going to have to dig into the analog trigger this offseason!