Hello!
I’m new in using DMA FIFO. I need to input an array into the FPGA VI. And then inside the FPGA VI, I get the sum of the elements of the array. I “send” this sum back to the Host VI. This should be simple. Unfortunately, I’m having problems. It seems that I’m not able to input the array into the FPGA VI. This is because nothing reflects in the “array” indicator inside the FPGA VI. Attached are the pictures of the Host VI and FPGA VI. Please assume that I have already set the FPGA target so that there is no broken line in the Host VI block diagram.
Thank you so much for your time! 
