Multiple SPI Gyros

[siddharthjain03]

Hi, I’m trying to collect information from 2 gyros. We made an SPI Y cable with ID 0 and 1 and plugged one into each ADXRS450 gyro. We constructed them in C++:

 gryo1 = new frc::ADXRS450_Gyro(frc::SPI::kOnboardCS0);
 gryo2 = new frc::ADXRS450_Gyro(frc::SPI::kOnboardCS1);

However, after multiple tests, we found that we are only able to read heading from the Gyro that is created first in the constructor. We tried connecting one gyro to the MXP board and one to the SPI port and had the same result. We confirmed that both SPI cables and gyros work.

[tkchan]

Can you show your actual wiring diagram? did you wire each individual CS pin to the respective SS pin on the Gyro?

[Peter_Johnson]

There is only one SPI accumulator engine in the FPGA, so only one SPI gyro will work. A few years ago the FPGA didn’t have support for SPI accumulation, so there was a software implementation that would have allowed multiple SPI gyros (at high CPU cost), but that was removed when the FPGA support was added.

[siddharthjain03]

Ok, thank you for the information!

[MamaSpoldi]

It does make one wonder why there are options for multiple chip select addresses (ie. CS0, CS1, CS2, CS3) in addition to having 2 options for where to plug devices into the SPI when it is not possible to read more than one SPI device. Since this is a software limitation, at a minimum, the WPILib documentation should make it clear that although there are several address options it is only possible to instantiate one SPI device.

[Peter_Johnson]

You can have multiple SPI devices, and you can put a gyro on any of those ports. The limit of 1 applies only to gyro devices that use the periodic read feature in the FPGA to offload the processor (prior to this a single gyro could take as much as 40% CPU and be overall less accurate than the FPGA hardware implementation due to timing jitter). The limit of 1 for these devices has been added to the documentation.