We would like to set the low-pass filter on our gyro to match the digitizing rate of the A/D converters. Presumably this is also the rate at which the angle accumulator is updated.
One would like to avoid excessive aliasing on one hand and excessive phase shift on the other.
Does anyone know how fast that loop operates in the FPGA?
The FPGA sample rate is 153kHz.
That’s going to be the maximum analog rate. The rate per channel will be that divided by the number of open channels.
Details of the Analog implementation can be had from jhersh, the FPGA software designer, and EricVanWyk the hardware designer of the Analog Breakout.
Thanks for the information and the contacts.
The firmware may or may not be taking readings at the hardware’s maximum conversion rate. But if conversions are being done at max speed and they are all being averaged before use in the accumulator, we could use a very high analog cutoff frequency without any problem.