Reading Duty Cycle from DIO via FPGA

Anyone know how to extract duty cycle values from the DIO via the FPGA ? Does anyone have any example code.

The FPGA read/write control VI when linked to the RoboRIO Reference provides a DIO.PWMDutyCycleA


I have no idea how this works. But it seems like it will work. I just don’t know how to tell the RIO what DIO channel I’ve connected the encoder to.

Trying to read a Mag encoder with PWM output similar to CTRE’s mag encoder. Prior to this, when we used the CTRE mag encoder, we plugged our CTRE mag encoder into a canifier and the canifier API’s had a VI that would output duty cycle.

Trying to avoid the canifier, I was hoping to plug the PWM signal directly to a DIO channel in the RIO and program in labview some means of reading the duty cycle or pulse length.

The best I can find is in the Manual under Digital IO which talks about the minimum pulse width for the IO being 20ns.

Page 4:

That control is for PWM outputs, not PWM inputs. There is currently no FPGA support for PWM inputs, although it’s being looked at for 2020.

Thanks. So Canifier is our only option then?

In the meantime you may be able to use two Counters reading the same port to derive a duty cycle. See this discussion on FIRST Forums (the code is Java but the concept should still work).

Am I correct that this was not actually added for 2020?

This was added for 2020. It’s called DutyCycle, and it was added to all 3 languages.

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