Most people know that the rio has a Xilinx Zynq SoC, and it’s integrated FPGA is usually referred to as “the” rio FPGA, but it actually has another: a Lattice MachXO2-640. Does anyone know what it might be for? Peter (WPILIB) suggested maybe power sequencing or UVLO which would make sense since it’s non-volatile and boots quickly.
I found it while messing around with the rio JTAG port:
Info : JTAG tap: auto0.tap tap/device found: 0x012b9043 (mfg: 0x021 (Lattice Semi.), part: 0x12b9, ver: 0x0) Info : JTAG tap: zynq_pl.bs tap/device found: 0x23727093 (mfg: 0x049 (Xilinx), part: 0x3727, ver: 0x2) Info : JTAG tap: zynq.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x4)