The roboRIO has two FPGAs?

Hi everyone! Digital engineer here at NI. Loving and impressed by the post!
One thing not obvious about our use of the Lattice CPLD, if your curious, is that we also implement a watchdog timer in its LUTs/Registers. It is a nice independent device that can be configured to reset the processor in case it or an application on it crashes for whatever reason.


Wow, awesome to get a reply from an engineer at NI! Thank you!

Is the I/O watchdog that disables all outputs (CAN, PWM, Relays, etc) if not fed also implemented in the Lattice?

For IO, no that’s all in the normal FPGA. I imagine that watchdog is for if the CPU locks up, like could happen in an RT system.

CAN is special, how it’s watchdog works is device dependent.



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Only tangentially related but I didn’t wanna make a new topic just for this: PCB Arts put a Zynq on a Feather.

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Can you tell which Zynq it is? There are a few similar products out there, including this one in a Pi form factor:

Oh neat, I hadn’t seen that.

It looks like a xc7z007s-clg400. There isn’t too much info about it online, I would check out their Twitter if you’re curious. Looks like it will be open source at some point.

Edit: yeah it’s definitely an XC72007S-CLG400.

I’ll be interested to see the price point. You can get Zynq boards for pretty cheap:
But of course the Z7000 is a pretty far cry from the Z7020 in the RIO.

Single-core with a slightly slower clock and a fraction of the logic elements, but it’s still pretty insane for a Feather-sized board. RAM and thermals are also probably a bottleneck.

It’s not so much the exact specs that are interesting to me, it’s just neat that this stuff is being worked on in the open. I haven’t seen many open source Zynq boards that aren’t using a SoM (there is stuff like the CIAA-ACC already).